View NJU26102_71415.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NJU26102
www..com
General Description
Digital Signal Processor for TV Package
The NJU26102 is a digital signal processor that provides Delay, eala, ViVA2+, PEQ, and AGC. The NJU26102 is suitable for audio products such as TV, CD radio- cassette, speakers system, and others.
FEATURES
- Software * 3D sound : eala (NJRC Original Surround), BBE ViVA, BBE ViVA+ * Sound Enhancement: : BBE, BBE Mach3Bass * AGC * 5Band PEQ * Tone Control * Audio Delay ( fs=48kHz : Max. 25ms, fs=44.1kHz : Max. 27ms, fs=32kHz : Max. 37ms ) * Master Volume * WatchDog Clock Output
NJU26102FR1
- Hardware * 24bit Fixed-point Digital Signal Processing * Maximum System Clock Frequency : 38MHz Max. * Digital Audio Interface : 3 Input ports / 3 Output ports * Digital Audio Format : I2S 24bit, Left- justified, Right-justified, BCK : 32/64fs * Master / Slave Mode : Master Mode MCK 1/2 fclk, 1/3 fclk ex. MCK = 384Fs(1/2) or MCK = 256Fs(1/3) at fclk=768Fs * Power Supply : 2.5V * Input terminal : 3.3V Input tolerant * Package : QFP32-R1 (Pb-Free) * Two kinds of micro computer interface : I2C bus (standard-mode/100kbps) : Serial interface (4 lines: clock, enable, input data, output data)
The detail hardware specification is described in the " NJU26100 Series Hardware Data Sheet".
Ver.2006-11-27
-1-
NJU26102
www..com
Function Block Diagram
AD1/SDIN AD2/SSb
NJU26102
DSP ARITHMETIC UNIT SERIAL AUDIO INTERFACE BCKO LRO 24-BIT x 24-BIT MULTIPLIER ALU L/R SDO0~ SDO2 SDI0~ SDI2 BCKI
SCL/SCK
SDA/SDOUT
SERIAL HOST INTERFACE
PROGRAM CONTROL
RESETb MCK XI XO TIMING GENERATOR ADDRESS GENERATION UNIT
LRI
DELAY RAM
DATA RAM
FIRMWARE ROM
GPIO AND CONFIGURATION INTERFACE
SEL1
Fig. 1 NJU26102 Block Diagram
DSP Block Diagram
SW2 SDI0 SW1 SDO1 SDO0
Delay
SDI1 Trim SW4 SW3 SDI2 SW5 SW6 SW7
3D
Enhancement
EQ
eala(stereo) AGC *1 Simulated Stereo BBE ViVA (3D, BBE)
BBE
BBE Mach3 Bass
AGC *2
5Band PEQ HPF + 4PEQ T.C. + 3PEQ HPF+T.C. +2PEQ
SW8
BBE ViVA+ (3D, BBE, Mach3Bass) BBE ViVA2+ (3D, BBE, Mach3Bass, AGC)
Master Vol.
SW10
SDO2 SW9
AGC *3 Note 1. only one AGCs(*1, *2, *3) should be used. Note 2. Do not use *1AGC and *3AGC during BBE ViVA2 being in use.
Continuous Siginal Det.
WDC
CLOCK GENERATOR
Fig. 2 NJU26102 Function Diagram
-2-
Ver.2006-11-27
NJU26102
www..com
VDDR VDDR VDDC
18
24
23
22
21
20
19
SDI0 SDI1 SDI2 LRI BCKI MCK BCKO LRO
25
17
VDDC
VSSR
VSSR
VSSC
VSSC
Pin Configuration
16 26 15 27 14 28
WDC VSSC VDDC RESETb VSSO XO XI VDDO
NJU26102
13 12 11
31
30
29
10 32 9
1
2
3
4
5
6
7
SCL/SCK
Fig. 3 NJU26102 Pin Configuration
Pin Description
Table 1 Pin Description
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol SDO2 SDO1 SDO0 SEL1 *1 SCL/SCK SDA/SDOUT AD1/SDIN AD2/SSb VDDO XI XO VSSO RESETb VDDC VSSC WDC *2 I/O O O O I I I/O I I -I O -I --O Description Audio Data Output 2 L/R Audio Data Output 1 L/R Audio Data Output 0 L/R Select I2C or Serial bus I2C Clock / Serial Clock I2C I/O / Serial Output This pin requires a pull-up resistance. I2C Address / Serial Input I2C Address / Serial Enable OSC Power Supply +2.5V X'tal Clock Input OSC Output OSC GND RESET (active Low) Core Power Supply +2.5V Core GND Clock for Watch Dog Timer No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Symbol VDDC VSSC VDDR VSSR SDI0 SDI1 SDI2 LRI BCKI MCK BCKO LRO I/O Description Core Power Supply +2.5V Core GND I/O Power Supply +2.5V I/O GND Audio Data Input 0 L/R Audio Data Input 1 L/R Audio Data Input 2 L/R LR Clock Input Bit Clock Input Master Clock Output Bit Clock Output LR Clock Output
SDA/SDOUT
AD1/SDIN
AD2/SSb
SDO2
SDO1
SDO0
SEL1
8
----I I I I I O O O
* I : Input, O : Output, I/O: Bi-directional *1 SEL1 : Input *2 WDC : Output
Ver.2006-11-27
-3-
NJU26102
www..com
Digital Audio Interface
The NJU26102 audio interface provides industry standard serial data formats of I2S, MSB-first left-justified or MSB-first right-justified. The NJU26102 audio interface provides three data inputs, SDI0, SDI1, SDI2 and three data outputs, SDO0, SDO1, SDO2 as shown in table 2, table 3 and Fig.2. An audio interface input and output data format become the same data format.
Table 2 Pin No. 25 26 27 Table 3 Pin No. 3 2 1
Serial Audio Input Pin Symbol Description SDI0 Audio Data Input 0 L / R SDI1 Audio Data Input 1 L / R SDI2 Audio Data Input 2 L / R
Serial Audio Output Pin Symbol Description SDO0 Audio Data Output 0 L / R SDO1 Audio Data Output 1 L / R SDO2 Audio Data Output 2 L / R
Host Interface
The NJU26102 can be controlled via Serial Host Interface (SHI) using either of two serial bus format : 4-Wire serial bus or I2C bus.(Table 4) Data transfers are in 8 bit packets (1 byte) when using either format. Serial Host Interface Pin Description.(Table 5) Table 4 Serial Host Interface Pin Description
Pin No. 4 Symbol SEL1 Setting "Low" "High" Host Interface I C bus 4-Wire serial bus
2
Table 5 Serial Host Interface Pin Description Symbol 4-Wire Serial bus Format Pin No. I2C bus Format (I2C bus / Serial) 5 SCL / SCK Serial Clock Serial Clock Serial Data Input/Output Serial Data Output 6 SDA / SDOUT (Open Drain Input/Output) (CMOS) 7 AD1 / SDIN I2C bus address Bit1 Serial Data Input Serial enable 8 AD2 / SSb I2C bus address Bit2 Note : SDA /SDOUT pin is a bi-directional open drain. SDA /SDOUT output is normal CMOS output in case of 4-Wire Serial bus mode and SSb="Low". SDA /SDOUT output is Hi-Z state in case of 4-Wire Serial bus mode and SSb="High". This pin requires a pull-up resister in both 4-Wire serial and I2C bus mode.
-4-
Ver.2006-11-27
NJU26102
www..com
I C bus
2
When the NJU26102 is configured for I2C bus communication during the Reset initialization sequence. I2C bus interface transfers data to the SDA pin and clocks data to the SCL pin. AD1 and AD2 pins are used to configure the seven-bit SLAVE address of the serial host interface. (Table 6) This offers additional flexibility to a system design by four different SLAVE addresses of the NJU26102. An address can be arbitrarily set up by the AD1 and AD2 pins. The I2C address of AD1/AD2 is decided by connection of AD1/AD2 pins. Table 6 I2C bus SLAVE Address
AD2 AD1
bit7 0 0 0 0
bit6 0 0 0 0
bit5 1 1 1 1
bit4 1 1 1 1
bit3 1 1 1 1
bit2 0 0 1 1
bit1 0 1 0 1
R/W bit0 R/W
Start bit
Slave Address ( 7bit )
R/W bit
ACK
* SLAVE address is 0 when AD1/2 is "Low". SLAVE address is 1 when AD1/2 is "High". Note : In case of the NJU26102, only single-byte transmission is available. The serial host interface supports "Standard-Mode (100kbps)" I2C bus data transfer.
4-Wire Serial Interface
The serial host interface can be configured for 4-Wire Serial bus communication by setting SEL1 pin ="High" during the Reset initialization sequence. SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin. Data transfers are MSB first and are enabled by setting the Slave Select pin Low ( SSb=0 ). Data is clocked into SDIN on rising transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte (MSB) which is latched on the falling transitions of SSb. SDOUT is Hi-Z in case of SSb = "High". SDOUT is CMOS output in case of SSb = "Low". SDOUT needs a pull-up resistor when SDOUT is Hi-Z.
SSb SCK SDIN SDOUT Hi-Z bit7
MSB
bit6 bit6
bit5 bit5
bit1 bit1
bit0
LSB
bit7
bit0
unstable
Hi-Z
Fig. 4 4-Wire Serial Interface Timing Note: When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the transition of SSb="High". When the data-clock is more than 8 clocks, the last 8 bit data becomes valid. After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes "High". SDOUT is Hi-Z in case of SSb = "High". SDOUT is CMOS output in case of SSb = "Low". SDOUT needs a pull-up resistor to prevent SDOUT from becoming floating level.
Ver.2006-11-27
-5-
NJU26102
www..com
WatchDog Clock
The NJU26102 outputs clock pulse through WDC (No.16) pin during normal operation. The output toggle cycle (Low/High) from a WDC pin changes with sampling frequencies. (Table 7) Table7 WatchDog Clock Output Cycle Sampling Frequencies WDC Output Cycle (Low/High) Time 32 KHz 276ms 44.1KHz 200ms 48 KHz 184ms The NJU26102 generates a clock pulse through the WDC terminal after resetting the NJU26102. The WDC clock is useful to check the status of the NJU26102 operation. For example, a microcomputer monitors the WDC clock and checks the status of the NJU26102. When the WDC clock pulse is lost or not normal clock cycle, the NJU26102 does not operate correctly. Then reset the NJU26102 and set up the NJU26102 again. Note: If input and output of a audio signal stop and an audio interface stops, WDC can't output. That is because it has controlled based on the signal of an audio interface.
-6-
Ver.2006-11-27
NJU26102
www..com
NJU26102 Command Table
Table 8 NJU26102 Command No. Command
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 System State Firmware Version No. Request Firmware Mode Select Input Select / Fs Select Input Trim Master Volume Channel Balance AGC Threshold Level eala Gain BBE ViVA / ViVA+ Surround Gain BBE BBE ViVA2+ AGC BBE Mach3Bass EQ Mode PEQ f0 / HPF fc Delay Time Continuous Signal Detect NOP
Notes : In respect to detail command information, request New Japan Radio Co., Ltd. and permission of a licenser ( BBE Sound, Inc.) is required. .
Ver.2006-11-27
-7-
NJU26102
www..com
License Information
1. The NJU26102 is manufactured by New Japan Radio Co.,Ltd. under license from BBE Sound Inc. BBE is a registered trademark of BBE Sound Inc. A license from BBE Sound Inc. must be required before the NJU26102 can be purchased from New Japan Radio Co.,Ltd.
BBE Sound, Inc. 5381 Production Drive Huntington Beach, CA 92649 USA Tel: 714-897-6766 Fax: 714-896-0736
http://www.bbesound.com
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
-8-
Ver.2006-11-27

▲Up To Search▲

Price & Availability of NJU26102

	To Download NJU26102 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .